TSMC launches new A16 wafer fabrication technology, mass production expected in 2026
Time:2024-04-26
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The TSMC Technology Forum 2024 is a major technology event where TSMC unveiled a series of innovations such as its latest process technologies, advanced packaging technologies, and three-dimensional integrated circuit (3D IC) technologies.
TSMC made its first public disclosure of a process technology called TSMC A16 (1.6nm) at the forum.
TSMC A16 (1.6nm) technology performance indicators organized:
1, process technology: TSMC A16 uses 1.6nm process technology, which is currently one of the industry‘s leading process technologies, designed to provide higher performance and lower power consumption.
2, super rail technology: This technology moves the power supply network from the back of the wafer, freeing up more space for the layout of the signal network on the front of the wafer, thus improving logic density and performance. This design makes the A16 particularly suitable for high-performance computing (HPC) products with complex signal wiring and dense power supply network.
3, performance and power consumption: compared with the N2P process, TSMC A16 in the same operating voltage (Vdd), the speed increase of 8-10%. And at the same speed, its power consumption is reduced by 15-20%. This means that the A16 can maintain high performance while more effectively controlling power consumption, thereby extending the life of the device and reducing heat dissipation problems.
4, chip density: TSMC A16 chip density compared to the N2P process to improve up to 1.10 times. This means that in the same physical space, A16 can accommodate more transistors and other electronic components, further enhancing its performance and computing power.
TSMC Technology Forum 2024, Eight Technologies:
1. TSMC A16, TSMC‘s innovative NanoFlex technology supporting nanosheet transistors, N4C technology, CoWoS, system-on-chip integration, as well as system-on-wafers (TSMC-SoW), silicon photonic integration and automotive advanced packaging.
2. TSMC A16: This is TSMC‘s first publicly available process technology, which utilizes a 1.6nm process combining super rail architecture and nanoscale chip transistors, and is expected to be in mass production in 2026. Compared to the N2P process, A16 chip density is increased by up to 1.10 times, speed is increased by 8-10% at the same operating voltage, and power consumption is reduced by 15-20%.
3. NanoFlex Technology: This is the technology paired with TSMC‘s upcoming N2 process, providing chip designers with flexible standard components. Lower-height components save area and have higher power efficiency, while higher-height components maximize performance. Customers are able to optimize the combination of high and low components within the same design block, adjusting the design to achieve the best balance between power, performance and area for the application.
4. N4C Technology: This is a continuation of TSMC‘s N4P technology and is expected to be in mass production in 2025. With up to 8.5% lower die cost and low adoption threshold, it helps provide a cost-effective option for value-oriented products.
5. CoWoS Technology: This is an advanced packaging technology that seamlessly integrates advanced processing units such as GPUs and AI gas pedals with High Bandwidth Memory (HBM) modules, reducing interconnect latency between homogeneous or heterogeneous logic SoCs as well as between HBMs. This technology helps improve system reliability, lifetime and power integrity while reducing size and cost.
6. System-on-Chip (TSMC-SoIC): This is an innovative wafer-level packaging technology that integrates multiple small chips into a single system-on-chip with a smaller area and thinner profile. This technology enables heterogeneous 3D integrated circuits with high speed, high bandwidth, low power consumption, high pitch density and minimal footprint.
7. System-on-Wafer (TSMC-SoW): TSMC‘s first SoW product that has been mass-produced utilizes logic wafer-based integrated fan-out (InFO) technology. A wafer-stacked version with CoWoS technology is expected to be ready in 2027, capable of integrating SoICs, HBMs, and other components to create a wafer-level system that is powerful and has computing power comparable to a data center server rack or even an entire server.
8. Silicon Photonics Integration: TSMC is developing Compact Universal Photonics Engine (COUPE) technology, which uses SoIC-X chip stacking technology to stack electronic die on top of photonic die, providing the lowest resistance and higher energy efficiency for the interface between the two compared to traditional stacking.
Automotive Advanced Packaging: Following the launch of the N3AE process to support automotive customers, TSMC is integrating advanced chips and packages to meet automotive customers‘ needs for higher computing power while meeting automotive safety and quality requirements.
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Elan Tsao