The Cyclone® IV FPGA family continues the leadership of the Intel® Cyclone® FPGA family by offering low-power FPGAs with transceiver options.Cyclone® IV FPGAs are suitable for cost-sensitive, high-volume applications and help you meet growing bandwidth requirements. This product family is recommended for edge-centric applications and designs.
Benefits
System cost optimization
All Cyclone® IV FPGAs require only two power supplies to operate, greatly simplifying power distribution networks, reducing board costs, board space, and design time. Leveraging the integrated transceivers on the Cyclone® IV FPGA architecture simplifies board design and integration. In addition, the flexible transceiver clocking architecture supports your implementation of multiple protocols while leveraging all available transceiver resources. With the integration features and flexibility of Cyclone® IV GX FPGAs, you can design smaller, lower-cost devices and reduce total system cost.
Lower Power Consumption
Built on an optimized 60 nm low-power process, the Cyclone® IV E FPGA continues the low-power leadership of the previous generation of Cyclone® III FPGAs, which lowered core voltage and reduced total power consumption by 25% compared to the previous generation. With Cyclone® IV GX transceiver FPGAs, you can bridge PCI Express* to Gigabit Ethernet with less than 1.5 watts of power.
Intel® Cyclone® IV FPGAs are optimized for the lowest power consumption to help you better meet thermal requirements. As a result, you can not only reduce or eliminate system cooling costs, but also extend the battery life of your handheld devices.
Cyclone® IV FPGA Power Consumption
The Cyclone® IV FPGA family demonstrates Intel‘s leadership in delivering power-efficient FPGAs. With enhanced architecture and silicon, advanced semiconductor process technologies and power management tools, Cyclone® IV FPGAs consume up to 25% less power than Cyclone® III FPGAs.
The table below shows the static power consumption of Cyclone® IV E devices at 85°C junction temperature. At 85°C, the smallest Cyclone® IV EP4CE6 device consumes as little as 38 mW, while the largest Cyclone® IV EP4CE115 device consumes as little as 163 mW.
Benefits of low power consumption
Reducing the power consumption of programmable logic devices offers unattainable advantages for many applications. However, reducing power consumption is only one aspect of system power consumption. The chart below shows that Cyclone® IV GX FPGAs can reduce FPGA power consumption by an average of 30%.
Chip and Architecture Optimization
Without the use of power reduction techniques, the use of submicron semiconductor processes can significantly increase static power consumption. The use of submicron process technology increases static power consumption due to increased leakage current thresholds.
Intel minimizes leakage current and thus reduces quiescent power consumption by employing the low power (LP) process technology typically used by leading semiconductor manufacturers for handheld components. This advanced process reduces physical size while combining architectural optimizations that help Cyclone® IV FPGAs minimize dynamic and static power consumption. Intel has implemented several process and architectural enhancements in Cyclone® IV FPGAs, including the use of low dielectric constant materials, variable channel length and oxide thickness, and multiple transistor threshold voltages.
Accurate Power Estimation and Analysis
Intel supports the most accurate and complete power management design tools for power estimation and analysis throughout the design conception to implementation process. Intel‘s tool suite provides up to 125°C operating temperature and worst-case chip power estimates for low-cost FPGA kit families. Intel provides the following power estimation and analysis resources:
Cyclone® IV Early Power Estimator. Intel® Quartus® Prime power analysis and optimization technology. Power Management Resource Center.
Power Analyzer is a more detailed power analysis tool that uses actual design layout wiring and logic configuration. Power Analyzer is a more detailed power analysis tool that uses actual design layout wiring and logic configuration. The tool uses simulated waveforms to accurately estimate dynamic power consumption. Overall, the power analyzer combines the use of accurate design information to estimate within ±10% accuracy. Intel® Quartus® Prime power consumption models are closely related to actual chip measurements.
Intel uses over 5,000 different test configurations to measure the power consumption of each component in the Intel® Cyclone® family of FPGAs. Each configuration is primarily used to measure a particular circuit composition of the FPGA in a particular configuration.
Intel® Quartus® Prime Power Optimization
Detailed design implementation can improve performance, reduce size, and lower power consumption. In the past, performance and size were automatically balanced within the register transfer level (RTL) through the layout routing design flow.
Intel® Quartus® Prime software power optimization tools automatically use Cyclone® IV FPGA architecture features to reduce dynamic power consumption by 25% compared to Cyclone® III FPGAs.
Many of the automatic power optimization features of Intel® Quartus® Prime software are transparent to the designer and enable optimal utilization of the FPGA architecture to reduce power consumption. For example, with Intel® Quartus® Prime software, you can:
Convert major functional modules.
Mapping user RAM to reduce power consumption. Reprogram logic to reduce dynamic power consumption. Select logic inputs correctly to minimize capacitance in high-frequency trigger networks. Reduce the area and wiring requirements of the core logic to minimize the dynamic power consumption of the wiring. Modify the layout to reduce clock power consumption.
Cyclone® 10 FPGAs, part of Intel® Edge-Centric FPGAs, Intel® Cyclone® 10 low-power devices are optimized for cost-sensitive applications, balancing power and bandwidth, while the Intel® Cyclone® 10 GX device family is optimized for applications with higher bandwidth and performance.
Intel® Cyclone® 10 GX FPGAs
Benefits
Improves productivity, increases integration and reduces time-to-market.
Enables ultra-short compile times for 20nm devices while providing an advanced design environment for low-cost FPGAs.
Supports partial reconfiguration and advanced features such as single particle flip-flop (SEU) for error correction and detection.
Shorter compile times enable faster design iterations and faster timing convergence.
Intel® FPGA SDK 1 for OpenCL™- C-based design input that provides an easy-to-implement design environment on FPGAs.
Platform Designer (formerly Qsys) - System-level design environment.
DSP Builder for Intel® FPGAs - Model-based DSP environment within the MATLAB*/Simulink* environment.
Applications
Machine Vision
Designers are challenged with the need for ever-increasing sensor resolution, local video analysis requirements, high-capacity frame storage, and evolving interface standards for host processors.
In addition to providing faster transceiver speeds up to 12.5 Gbps and supporting evolving camera interfaces, Intel® Cyclone® 10 GX devices offer integration of numerous vision features such as image capture, scaling, high performance pre-processing and communication capabilities. These features enable machine vision designers to develop faster time-to-market strategies.
Smart Vision
Combined with computer vision and Intel® architecture, Intel® Cyclone® 10 GX FPGAs support heterogeneous computing platforms, which in turn enable optimal execution of image sensor pipelines and vision analysis algorithms in a holistic system. While the Intel® architecture simplifies design with the OpenVINO™ toolkit, the Intel® Cyclone® 10 GX device family enables acceleration of complex algorithms such as motion detection, facial recognition, and object detection.
Learn more about Intel FPGA support for embedded vision applications on the Smart Vision and Video page.
Industrial Fog Computing in SDA Environments
Industrial fog computing for software-defined automation (SDA) requires scalable computation, acceleration, and flexible connectivity on plant-level fog, cell-level fog, and machine fog nodes (MFNs).
At the plant level, the main SDA component is the process orchestration of the resources under it. This places requirements on cell-level fog nodes and MFNs that should change roles based on the requirements specified by process orchestration software such as Wind River Titanium Server. As a result, hardware reconfiguration becomes a new requirement.
Meeting performance, latency and total controller power requirements requires processor workload offload and acceleration. Examples include cryptographic acceleration, machine learning (classification and training), and accelerated processing of streaming data (Apache Spark).
Finally, while the OPC Unified Architecture (OPCUA) based on Time Sensitive Networking (TSN) is the solution for interoperability and networking, it also supports traditional Industrial Ethernet and has the ability to swap to different Industrial Ethernet interfaces as needed.
The Intel® Cyclone® 10 GX device is the ideal mating chip for Intel® processors, enabling hardware reconfigurability through partial reconfiguration. It also enables workload acceleration through a fast FPGA architecture, flexible connectivity through programmable features, and significant performance gains and power savings.
Industrial Drivers
Unlike traditional motor control drive designs based on ASICs, ASSPs, microcontrollers, and DSP devices, drive systems based on an Intel® FPGA platform (shown below) support platform scaling to meet a variety of drive requirements.
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Elan Tsao